The present invention relates to a digit-serial arithmetic system.
U.S. Pat. No. 5,016,011 shows a digit-serial arithmetic system in which a data word is partitioned into a plurality of, for example, 4-bit digits. This type of digit-serial arithmetic system has the capability to provide high throughput performance by making use of the advantages of both the word-parallel architecture and the bit-serial architecture.
In digital signal processors (DSPs), it is necessary to carry out operations on various types of words having different numbers of bits. Therefore, in order to realize a digit-serial DSP, it is necessary to make a change in the configuration of the digit-serial DSP according to a change in the number of digits forming a data word. However, the above-described digit-serial arithmetic system is unable to make a change in its configuration with flexibility.